Note: This article was originally posted on LinkedIn in December 2019 and was later posted on this blog with a backdated publishing date
I will unfortunately not make it to the RISC-V summit this year, but since everyone will be talking about RISC-V this coming week I thought it would be a good opportunity to highlight some of the work I have done this year within RISC-V and FOSSi (Free and open source silicon) in general. And you are more than welcome to contact me if you are interested in knowing more about any of this work or other things related to RISC-V, FOSSi or Qamcom
SweRVolf
Western Digital made a big splash last year when they announced the release of the open source RISC-V CPU SweRV EH1, currently the fastest 32-bit RISC-V CPU available. Together with Western Digital I have created SwerRVolf, an open source portable and extendible SoC using the SweRV EH1. The intention with this SoC is to allow users interested in SweRV to quickly get started running software or building their own customized SoC using SweRV. The whole project is open source and can be run in a simulator or on supported FPGA targets. On the software side it can be used to run Zephyr OS and has debugging support. The code is available at https://github.com/chipsalliance/Cores-SweRVolf More features will come in 2020 so make sure to check in regularily. The project has also been featured in presentations at the inagural CHIPS Alliance workshop as well as the CHIPS Alliance tools November workshop in Munich. During the latter there was also a tutorial aimed to get people started using the SoC. This workshop is also freely available and I'm happy to do variations on this within your company if you want to get started with a RISC-V SoC.
SERV
In case you're not aware, I have created SERV, likely the world's smallest RISC-V CPU and still cabable of running Zephyr OS. SERV was originally created for the 2018 RISC-V SoftCPU contest, but I have kept working on the core during 2019. In April I submitted a presentation for the RISC-V workshop in Zürich called "Bit by bit - how to fit 8 RISC-V cores on a $38 FPGA board". When there was time to do the actual presentation I had to update the title since further optimizations had allowed me to fit 16 cores on the same board. Work continued after that and in November I was able to fit 53 RISC-V cores on a $30 FPGA board. The SERV CPU is of course open source and available here https://github.com/olofk/serv If you want to learn how to build SERV into your designs and why you should do it, just reach out and I'll get you up to speed.
FuseSoC
FuseSoC is a package manager for IP cores. It is created to manage and describe collections of open source and proprietary cores so that they can be put together to make a SoC. FuseSoC has been around for eight years now, but the past year has seen a lot of improvements and a massive growth of available IP cores (over 500 cores!) to use with FuseSoC. This year it has also been adopted by some major Open source silicon projects such as the manycore OpenPiton project from from Princeton and OpenTitan, the industry collaboration project to create a fully open source Root of Trust device. Even though there are a large number of RISC-V based projects using FuseSoC it is used in many places as well, most notably this year is perhaps the open source POWER implementation called MicroWatt released this summer. If you want help with packaging your RISC-V core to be available for FuseSoC users or if you want to use FuseSoC within your company to manage your IP cores, just let me know. FuseSoC can be found here https://github.com/olofk/fusesoc
Edalize
Closely related to FuseSoC is Edalize, which originally was part of FuseSoC but now a project of its own. Edalize is a build tool abstraction which provides a common interface to the supported EDA tools. It can be used to e.g. target different simulators with a flick of a switch or easily run the same design on FPGA and simulation targets. This year has seen many improvements and support for three new tool flows, which brings up the number of supported tools to 17. Most of this work has been done by contributors, which is a great indicator that it is actively used by many people. See more here https://github.com/olofk/edalize If you're a user or a tool vendor and feel that your favorite tool is missing, just let me know and we can discuss how to add it.
Observer
By combining the flexibility of FuseSoC with the resource efficiency of SERV I created a project called Observer. Observer is a software-programmable sensor aggregation platform for heterogenous sensors, combining the best of HW and SW in an FPGA. It is built on the idea that FPGAs are excellent for communicating with various types of external devices, but many types of data processing are best done in software. By pairing a SERV CPU to each sensor it is possible to combine the speed of RTL with the flexibility of software to easily build a sensor fusion system. The project is still in early stages, but works on a supported FPGA platform already and as a proof of concept it has been shown possible to collect data from over 50 different sensors simultaneously, each with their dedicated RISC-V CPU to handle data. Code can be found here https://github.com/olofk/observer If you want to customize Observer for your particular use case I'm happy to talk more.
Qamcom joins RISC-V Foundation
This year Qamcom joined the RISC-V Foundation. As our first exercise upon joing the foundation, we teamed up with RISC-V veterans SiFive to host the SiFive Tech Symposium in Stockholm in May. At this event we highlighted how we see that RISC-V can benefit many of the areas where we provide expert knowledge, such as AI, automotive, RADAR and 5G. If you are interested in what services Qamcom can provide within these areas and other, feel free to contact me or any of my colleagues or read more about us on https://www.qamcom.se/
Qamcom joins CHIPS Alliance
RISC-V is getting a lot of attention, but an open source ISA is just one of the many challenges we are facing when it comes to innovating chip design. We see an increasing need for custom silicon for many of our clients and partners and there are many keys to unlock to achieve this. CHIPS Alliance is an important consortium with a combination of small and large forward-thinking companies that aims to make open source silicon viable by collaborating on common cores, tools and infrastructure. If you want to be part of the CHIPS Alliance to accelerate chip design, go to https://chipsalliance.org/ to learn more.
Qamcom joins Mentor OpenDoor
Mentor, a Siemens business, has a partner program called OpenDoor. Both Mentor and Qamcom sees the importance of high quality verification of open source silicon and by joining this program, we will ensure that the work we do within open source silicon has first-class support for Mentor's EDA tools to allow new and existing users of these tools to quickly get started using open source IP cores in their products.
FOSSi Foundation
In 2015 I co-founded the FOSSi Foundation with a mission to promote and assist open source silicon in the industry, academia and for hobbyists. FOSSi Foundation consists of many people who work across all levels to acheive these goals but my personal involvement this year has mostly focused on creating events to bring people from industry, academia and hobbyists together under a single roof to exchange experiences. As usual we had ORConf in Europe but we also teamed up with the RISC-V Foundation to create the Week of Open Source Hardware (WOSH) in Zürich conjoined with the RISC-V workshop there. During the event I presented SERV, a poster of FuseSoC and won an award for FuseSoC given by Eurolab4HPC. This was also the year when we did our first conference on US soil. In May we held a new event called Latch-Up in Portland, Oregeon which was a great sucesss. We are already planning for three events next year as well. First up is FOSSiStanbul in Istanbul, Turkey, followed by a new Latch-Up in Cambridge, MA and the usual ORConf some time in the fall. Check out https://fossi-foundation.org/events to see where you should book your tickets.
Apart from events I was also mentor for Google Summer of Code for the fourth year in a row. This year I co-mentored Nancy Chauhan who worked with FOSSi Foundation and did a fantastic job to improve our CI platform at ci.librecores.org
Other stuff
I have had a long and troubling relationship with IP-XACT, as can be seen in my most cited article . I still stand by my point that we need some sort of standard for describing many of the aspects of IP cores that FuseSoC doesn't care about such as register maps and how to connect cores to each other. I haven't done much work in this area for a long time, but a presentation at Latch-Up by Aliaksei Chapyzhenka on a project called DuH prompted me to resume my efforts and I have now started working on combined IP-XACT/Duh tooling that I hope will be of interest. It's of course open source as well, but I haven't cleaned up enough to release it yet :) If you are an IP-XACT user or interested in tooling in this area, please let me know.
Wow! This turned out far longer than I expected. Seem I did a lot of stuff around RISC-V and Open source silicon in 2019. Let's see what the next decade will bring
Catch up at Latch-Up!
